Conventional trace buffer managers facilitate the probing of internal nodes of an integrated circuit design. With millions of internal nodes and typically less than 500 external pins, modern integrated circuit designs present a substantial challenge for engineers and technologists looking to debug circuit designs. It can be very difficult to see what transpires at the transistor level within a Very Large Scale Integration (VLSI) design.
A conventional Trace Buffer Manager (TBM) is an optional piece of hardware that can be implemented one or more times in the reference portion of an integrated circuit design. Each trace buffer manager that is implemented collects debug information from other units on the chip, multiplexes the debug information into a single I/O path, optionally applies simple filtering rules to the collection method, and logs the data into one or more random access memory units. In addition to being logged, the filtered data can be sent to an output bus which is optionally connected to external I/O pins to be monitored by a logic analyzer or other piece of hardware. Conventional approaches implement a trace buffer manager that has a dedicated bank of RAM or can access memory that is shared with other logic circuits through multiplexers. The memory implemented for the trace function is minimized to minimize die size and cost. The trace point paths in conventional designs are manually designed when the chip is laid out.
It would be desirable to implement a trace buffer manager that may be implemented (i) with allocated memory on the die that is not used by the reference design, (ii) without allocating dedicated RAM, (iii) to maximize the amount of memory available to the trace buffer manager, and (iv) to minimize wasted die real estate.